Physical and Digital Circuit Design Engineer (#6200-1045)

Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.

Job Description/Responsibilities

Are you ready to shape the future of technology? As a Physical Design Engineer, you will be a mastermind behind the physical manifestation of cutting-edge semiconductor designs. You will transform abstract concepts into tangible, high-performance hardware that powers the next generation of devices. Join us and turn visionary ideas into reality!

Primary Job Responsibilities

• Craft the Future – Lead the RTL to GDS journey, sculpting the landscape of chips that will power tomorrow's innovations.
• Solve the Puzzle – Tackle complex timing and power challenges, ensuring our designs not only meet but exceed performance expectations.
• Guard the Integrity – Be the final gatekeeper, conducting rigorous physical verification to ensure flawless functionality before the grand tape-out.
• Innovate and Automate – Push the boundaries of physical design by setting up state-of-the-art flows and automating processes for peak efficiency.
• Collaborate to Elevate – Work alongside a symphony of brilliant minds, integrating custom logic and IP to orchestrate a masterpiece of technology.

Preferred Skills

• Proficiency in using industry standard tools such as Fusion Compiler, IC Compiler II, Design Compiler,PrimeTime, Redhawk, Calibre, ICV, etc.
• Experience with floorplanning, placement, routing, timing closure, and power optimization.
• Experience with CTS optimizations, special clock routing rules, and cell placement related to jitter clock of PLL.
• Ability to perform physical verification checks such as DRC, LVS, ERC, etc. and debug issues.
• Understanding of low-power design techniques such as power gating, voltage islands, clock gating, etc.
• Proficient in a scripting language such as Tcl, Perl, Python, etc.
• Good communication and teamwork skills.

Education and Experience

• BS/MS in Electrical Engineering or Computer Science with 3-12 years experience.
• Track record of successful tape-outs and working knowledge of advanced FinFet technology nodes (16nm/7nm/3nm) and beyond.
• A maestro in EDA tools, scripting languages, and methodologies, orchestrating the physical design with precision and creativity.
• A problem-solver at heart.

Why Join Us?

• Impact – Your work will be at the core of products that revolutionize industries.
• Innovation – Immerse yourself in an environment that celebrates breakthroughs and encourages out-of-the-box thinking.
• Growth – Advance your skills with continuous learning opportunities and career development.

Ready to be a cornerstone in the edifice of technological progress? Apply now and carve your legacy in silicon!