Job Application for Fall Internship - Signal Integrity/Power Integrity Engineer at Astera Labs Early Career

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Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.

Job Summary:

At Astera Labs, we seek motivated SI/PI and System Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications.

Job Responsibilities:

In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations.
You will also formulate a comprehensive system validation plan and design experiments to root cause unexpected behavior, report results and specification compliance.

Required Skills:

Basic Qualifications:

Pursuing a bachelor's in electrical engineering
Strong background in electrical engineering
Self-starting, strong initiative, and can-do attitude.

Preferred Experience:

Familiar with SI and PI design challenges for high-speed interconnects
Hardware product design experience in networking, compute, or RF.
2D and 3D simulation experience with Cadence/Mentor/Ansys/ADS/etc. toolsets
EM modeling of connector structures
High-speed SERDES measurement, channel simulation, and equalization
Working knowledge of PCB fabrication limits and trade-offs
PI experience a bonus.
Working knowledge of key, high-speed design blocks such as PLLs, DFE, Tx EQ
Experience in system testing, characterization, margin analysis, and optimization of high-speed PCIe/CXL data links over long and short channels
In-depth understanding of DDR 4/5 protocols and JEDEC Standard.
Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Fall Internship - Signal Integrity/Power Integrity Engineer

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