Formal Verification Engineer (Intern 2026)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Role: You will be responsible for formal verification of high-performance design IPs/interconnects and memory subsystems that form the backbone of cloud and hyperscaler computing platforms. You will have direct impact on our design verification methodologies to improve design quality and enable on-time delivery of our products. You will be part of a world-class team that enables the next generation of generative AI and cloud hardware platforms. You will work closely with our silicon architects, design and verification engineers to architect and implement formal verification testbenches for complex microarchitectures and help develop and deploy state-of-the-art formal verification tools and methodologies.

Job description:

· Develop detailed FV test plans based on design specifications and work closely with design teams to improve micro-architecture specification methods.

· Identify critical IP logic and key micro-architectural properties that guarantee design correctness.

· Code and implement FV abstractions, models, assertions, and perform assertion model checking to uncover corner-case bugs.

· Implement FV complexity reduction techniques using EDA/academic FV tools to achieve proof convergence or sufficient proof depth.

· Develop and code scripts to improve FV productivity and efficiency.

· Assist designers in implementing assertions and FV testbenches for unit/block-level RTL.

· Attend design reviews and work closely with design teams to improve design interfaces and design quality (PPA) based on feedback from formal analysis of the microarchitecture.

Skills and Qualifications:

· Solid understanding of hardware micro-architectures, logic design, pipelined out-of-order execution engines and memory hierarchy sub-systems.

· Conversant with formal verification abstractions and complexity reduction techniques

· Knowledge of Verilog/SystemVerilog HDLs and System Verilog Assertions (SVA)

· Strong Tcl/Python/Makefile scripting knowledge

· Knowledge of Cadence or Synopsys or Siemens EDA FV tools or any academic FV tool

· Excellent logical and problem-solving skills.

· Strong debug skills with a hacker-like mindset to expose subtle architecture/RTL design bugs.

Minimum education and requirements:

·Pursuing BS/MS/PhD in ECE/CS/Math

· A passion to learn and to explore new frontiers in uncovering design bugs

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.