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Advanced Design Verification Engineer (Intern 2026)

San Jose, CA

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Job Description:  

As the Advanced Design Verification Engineer, you will lead next-generation ASIC infrastructure initiatives, including the development of tools and infrastructure targeting efficiency and reuse spanning DV, Emulation, pre, and post-silicon. Exposure to AWS cloud infrastructure and job schedulers such as SLURM, combined with strong Python programming proficiency, is a strong plus.

Basic Qualifications:  

  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance and supervision.  
  • Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!

Qualifications:  

In B.S. in CE/ EE. Working towards M.S. is preferred ASIC Emulation and/or DV experience Simulation/emulation platform experience with domain expertise in high-speed protocols PLI/DPI Programming/scripting languages: Perl/python/C/C++ for protocols like PCIe/CXL/DDR AWS cloud infastructure and job schedulers such as SLURM exposure
  • Experience in ASIC Emulation and/or Design Verification.  
  • Experience with simulation and emulation platforms with domain expertise in high-speed protocols. 
  • Experience working with PLI/DPI and other emulation interfaces.  
  • Experience in programming and scripting languages (like Perl/python/C/C++).
  • Experience in a role requiring interaction with senior leadership (e.g., Director level and above).  
  • Experience with high-speed protocols like PCIe/CXL.  
  • Experience in developing platform-agnostic transaction wrappers in C/C++ for protocols like PCIe/CXL/DDR.  
  • Currently based locally or open to relocation.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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