Semiconductor Packaging Engineer (Intern 2026)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Job Description:

As an Astera Labs Semiconductor Packaging Intern, you will be part of the packaging team that develops Astera Labs’ portfolio of connectivity products in the world’s leading cloud service providers and server and networking OEMs. You will work to enhance the key areas of package development cycles such as package design, modeling, automation flow, and documentation. You will also work cross-functionally to understand project requirements and develop solutions.  

Responsibilities: 

Basic qualifications:

• Working towards M.S. or PhD in Electrical Engineering or related field
• Cumulative 3.3/4.0 GPA, or higher
• Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of multiple tasks. Working with minimal supervision to deliver solutions in a fast-paced environment.
• Strong time management skills and strong written and verbal communication skills

Required experience:

• Coursework in RF/microwave, communication systems and signal analysis, semiconductor manufacturing, or circuit design.
• Understanding or coursework in signal and power integrity is a plus.
• Understanding or coursework in semiconductor packaging is a plus.
• Scripting or software development experience in popular programing languages such as Python, Visual Basic, or equivalent.

 Preferred experience:

• Experience with physical design or layout tools such as AutoCAD or Cadence Allegro is a plus.
• Experience of using 3D Electromagnetic simulation tools such as ANSYS is a plus.
• Knowledge of semiconductor multi-layer flip-chip package (FCBGA/FCCSP) is a plus.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.