ATE Test Engineer (Internship 2026)

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

We are looking for Test Engineers with experience in developing S/W solutions that control hardware. A deep understanding of C++, Python and computer architecture are a requirement. The ideal candidate will learn from the Astera Labs in-house experts to develop SoC production tests for any Astera Labs product. Expected job duties include developing test strategy, interacting with manufacturing partners, writing specific portions of the ATE program and implementing the ATE solutions. The candidate will grow into an ATE test engineer to own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5), Ethernet, Infiniband, DDR, NVMe, USB, etc.

Basic qualifications:

• Strong academic and technical background in electrical engineering. Pursuing Bachelor’s in EE is required, pursuing Master’s is preferred.
• Coursework including detailed C++ s/w design with microprocessor coding a plus.
• Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
• Professional attitude with ability to execute on multiple tasks.
• Strong team player with excellent communication skills to work alongside a team of high caliber engineers.
• Entrepreneurial, open-mind behavior and can-do attitude.

Required experience:

• Collaboration with design team to define test strategy, create and own test plan.
• Fluent in data processing using high level programming languages including familiarity with modern databases.
• Knowledge with PCB board design and validation techniques.
• Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – SCAN, MEMBIST, SerDes and other functional tests.
• Knowledge of control interfaces – I2C, I3C, SPI, MDIO, JTAG etc.
• Knowledge of high speed communication protocols operating at 16Gbps and higher.
• Semiconductor development coursework with firm understanding of the design flow and implementation.
• Experience with lab equipment including protocol analyzers and oscilloscopes.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.