IC Packaging Technologist

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

Job Description:

We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in 2.5D/3D packaging, signal and power integrity (SIPI), and chiplet technology, as well as experience scaling technologies to high-volume manufacturing. This role demands a deep understanding of advanced packaging architectures (such as CoWoS, interposers, WLP, and heterogeneous/chiplet integration) alongside strong expertise in SI and PI. The successful candidate will contribute to strategic roadmap execution and deliver package solutions into production.

Basic qualifications:

• M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline.
• 10 years of experience in IC packaging development with deep exposure to SIPI and 2.5D/3D integration technologies.
• Hands-on experience with CoWoS, interposers, WLP, chiplet-based integration.
• Proficiency in SIPI tools: HFSS, Siwave, ADS, HSPICE, etc.
• Hands-on experience in high-frequency measurement and characterization with such as VNA.
• Expert knowledge of EDA design tools: Cadence Allegro/APD, Altium, etc.
• Entrepreneurial, open-mind behavior and hands-on work ethic with the ability to prioritize a dynamic list of multiple tasks.

Required experience:

• Proven experience in end-to-end IC packaging development for advanced packaging: CoWoS, interposers, WLP, chiplet-based integration.
• Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G PAM4 and beyond.
• Strong background in package SIPI for ultra-high-speed interfaces (up to 448G), including: SERDES, Ethernet, DDR, Die-to-Die (e.g., BoW or UCIe).
• Demonstrated success leading die-package-board co-design efforts, including packaging platform selection, stack-up and structure definition, signal and power integrity (SIPI) optimization, design for manufacturability (DFM), and driving designs through tape-out to volume manufacturing.
• Hands-on lab validation experience and simulation-correlation with high-frequency measurement (e.g., VNA, TDR).
• Extensive engagement with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development.
• Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation.
• Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing engineering teams.
• Exceptional technical collaboration with silicon design teams to define chip-to-chip integration flows, accounting for timing, power delivery, and physical package layout alternatives.

Preferred experience:

• Knowledge of mechanical, thermal, and electrical design trade-offs in package development is a plus.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.