Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Director, Hardware Design Engineering — AEC / SCM & China Customer Support

Reports to: Senior Director, Hardware Design Engineering

Location: Shanghai, China — Astera Labs Shanghai Design Center

About Astera Labs

Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our AEC and SCM product lines scale rapidly to meet hyperscale AI infrastructure demand — and as China-based OEM customers, hyperscale cloud providers, and system integrators increasingly adopt Astera Labs silicon and connectivity products — we are establishing a Shanghai-based hardware design center to drive product development, manufacturing collaboration, and customer engineering support in close proximity to our manufacturing partners and China-based customers.

About the Role

We are hiring a Director of Hardware Design Engineering — AEC / SCM & China Customer Support to establish and lead Astera Labs' Shanghai hardware design center. This role has dual mission ownership:

1. AEC & SCM Product Design — Primary ownership of Active Electrical Cable and Smart Cable Module hardware design execution, from architecture through production release, leveraging proximity to China-based cable assembly and module contract manufacturers

2. China Customer Engineering Support — Serving as Astera Labs' front-line hardware engineering partner for China-based customers (hyperscale cloud providers, server/switch OEMs, AI system integrators, cable/module manufacturers) who are integrating Astera Labs silicon into their own products or deploying Astera Labs AEC/SCM products in their infrastructure

Active Electrical Cables and Smart Cable Modules are the highest-volume, fastest-growing products in Astera Labs' portfolio — connecting GPUs, switches, and accelerators across AI clusters at 112G and 224G per lane. Simultaneously, China represents one of the world's largest and fastest-growing markets for AI infrastructure, with a dense ecosystem of OEM customers who require local, responsive hardware engineering support.

You will build and lead a multidisciplinary hardware engineering team in Shanghai — spanning electrical/flex/substrate design, mechanical engineering, hardware validation, and customer applications engineering — driving AEC/SCM product design excellence while serving as the trusted technical partner for Astera Labs' China customer base.

Reporting to the Senior Director of Hardware Design Engineering, you'll operate with significant autonomy on AEC/SCM product execution and China customer engagement while maintaining strategic alignment on technology roadmap, design standards, and customer priorities with the global engineering organization.

Key Responsibilities

Shanghai Design Center Leadership

• Establish, build, and lead Astera Labs' Shanghai hardware design center as the company's primary hub for AEC/SCM product design and China customer engineering support

• Recruit, hire, and develop a high-caliber multidisciplinary engineering team in Shanghai, including:

  • High-speed electrical/flex/substrate design engineers

  • Mechanical engineers (connector, housing, thermal, cable interface)

  • Hardware validation engineers

  • Customer applications/hardware support engineers

  • Lab/test engineers

• Define organizational structure, hiring roadmap, and operating model for the Shanghai center — balancing product design execution, customer support responsibilities, and global alignment

• Establish lab infrastructure in Shanghai to support AEC/SCM prototype bring-up, characterization, validation, failure analysis, and customer demonstration/interoperability testing

• Drive engineering culture that emphasizes design rigor, manufacturing awareness, customer responsiveness, and tight collaboration with Santa Clara headquarters and the Taiwan design center

• Serve as the senior Astera Labs engineering leader in China — representing the company with customers, manufacturing partners, suppliers, and industry stakeholders in the region

AEC Hardware Design

• Electrical & Substrate Design:

  • Own the electrical design of Active Electrical Cable products — including retimer integration on flex circuits or rigid-flex substrates, high-speed differential pair routing, power delivery, and passive component placement within severely constrained cable module form factors

  • Design high-speed interconnect substrates/flex circuits supporting 112G and 224G PAM4 signaling — achieving target insertion loss, return loss, crosstalk, and impedance control within compact AEC geometries

  • Drive power delivery network design for AEC products — ensuring clean, stable power to retimer silicon under all operating conditions within minimal board area and thermal constraints

  • Define and enforce AEC-specific design rules — including trace width/spacing, via structures, impedance targets, stackup configurations, and material selection for high-speed flex/rigid-flex substrates

  • Collaborate with Signal Integrity engineering to validate channel performance through simulation and measurement correlation across the full AEC link path

• Mechanical Design:

  • Direct mechanical design for AEC products — including connector mating interfaces (OSFP, QSFP-DD, or proprietary), housing/shell design, latching mechanisms, cable strain relief, overmold geometry, and cable-to-substrate transition structures

  • Drive thermal management design for AEC modules — ensuring retimer silicon remains within thermal limits across all deployment environments within compact housings

  • Ensure AEC mechanical designs meet relevant form factor and pluggable interface specifications with full dimensional compliance

  • Optimize mechanical designs for high-volume manufacturing — considering overmolding processes, housing injection molding, automated assembly compatibility, and cable handling requirements

  • Manage bend radius, strain relief, and cable exit geometry to ensure mechanical reliability under repeated plugging cycles and cable routing stresses

• Cable Interface & Assembly Design:

  • Define cable-to-substrate attachment methodologies — including soldering, welding, crimping, or other termination approaches that maintain signal integrity and mechanical reliability at high speed

  • Collaborate with cable suppliers and contract manufacturers on cable construction specifications — conductor gauge, dielectric materials, shielding architectures, and cable bundle configurations optimized for AEC applications

  • Design for cable assembly manufacturability — ensuring termination processes, alignment tolerances, and quality inspection points are compatible with high-volume production at CM sites

SCM Hardware Design

• Electrical & Module Design:

  • Own the electrical design of Smart Cable Module products — integrating retimer/re-driver silicon with advanced management, diagnostic, and monitoring capabilities on module-level substrates

  • Design SCM circuits that support intelligent link management features — including CMIS-compliant register interfaces, temperature/voltage monitoring, link health diagnostics, and firmware-driven equalization tuning

  • Ensure SCM electrical designs accommodate the additional complexity of management interfaces (I2C/I3C, SPI, UART) alongside high-speed data paths without compromising signal integrity

  • Drive power management design for SCM products — including voltage regulation, power sequencing, power monitoring, and power reporting capabilities

• Mechanical & Form Factor Design:

  • Direct mechanical design for SCM products — ensuring compliance with target pluggable form factors while accommodating additional components for smart/managed functionality

  • Design enhanced thermal solutions for SCM modules where additional silicon increases power dissipation beyond baseline AEC products

  • Ensure SCM mechanical designs maintain backward compatibility with standard connector interfaces while enabling differentiated functionality

• Smart/Managed Feature Integration:

  • Collaborate with Firmware Engineering to ensure SCM hardware designs support all required management features — including adequate GPIO, communication interfaces, non-volatile storage, and sensor connectivity

  • Design hardware hooks for manufacturing calibration, field diagnostics, and firmware update capabilities

  • Ensure SCM designs enable differentiated customer value through hardware features that support link health monitoring, predictive maintenance, and fleet-level cable management

China Customer Engineering Support

• Customer Design Enablement:

  • Serve as the primary hardware engineering interface for China-based customers who are integrating Astera Labs silicon (retimers, re-drivers, connectivity ASICs) into their own products — including server/switch OEMs, AI system integrators, cable/module manufacturers, and hyperscale cloud providers

  • Provide expert-level design review support for customer hardware designs — reviewing schematics, PCB/flex layouts, stackups, power delivery networks, thermal solutions, and signal integrity for products incorporating Astera Labs silicon

  • Deliver hands-on technical engagement during customer design cycles — from initial architecture consultation through prototype bring-up, debug, and production readiness

  • Develop China-specific reference design packages, application notes, and design guides — supplementing global collateral with region-specific considerations (local component availability, CM process capabilities, customer platform requirements)

  • Conduct design training workshops and technical seminars for customer engineering teams adopting Astera Labs silicon

• Customer Integration & Debug Support:

  • Support customer hardware bring-up, debug, and troubleshooting when integration challenges arise with Astera Labs silicon or AEC/SCM products — providing rapid, same-timezone technical response

  • Coordinate with internal teams (silicon, firmware, SI, validation) to provide root-cause analysis and corrective guidance for customer-reported issues

  • Support customer interoperability testing — helping customers validate Astera Labs AEC/SCM products or silicon within their specific platform configurations

  • Travel to customer sites across China to provide on-site design review, bring-up support, debug assistance, and integration guidance for critical programs

  • Maintain customer issue tracking, resolution timelines, and escalation processes — ensuring timely and high-quality support

• Customer Product Deployment Support:

  • Support China-based hyperscale customers deploying Astera Labs AEC/SCM products in production AI infrastructure — providing technical guidance on cable routing, thermal considerations, interoperability, and link optimization

  • Assist customers with AEC/SCM product qualification activities within their platforms — providing characterization data, reliability reports, and integration documentation

  • Help customers resolve field issues encountered during deployment scaling — coordinating with product engineering and manufacturing teams for rapid corrective action

  • Provide technical training for customer operations and deployment teams on AEC/SCM product handling, installation best practices, and link health monitoring

• Customer Relationship & Ecosystem Development:

  • Build deep, trust-based technical relationships with hardware engineering teams at key China-based customers — becoming their preferred and trusted technical partner for Astera Labs solutions

  • Partner with Sales, FAE, and Product Management teams to identify high-value customer engagements and prioritize hardware engineering support resources in China

  • Participate in customer roadmap discussions — providing hardware engineering perspective on future product requirements, platform evolution, and technology migration paths

  • Capture customer design challenges, feature requests, deployment feedback, and competitive intelligence — feeding these back into product roadmap, reference designs, and silicon requirements

  • Support joint development programs with strategic China-based partners — including co-designed products, custom form factors, and platform-specific optimizations

  • Engage with the China AI infrastructure ecosystem — attending industry events, building supplier relationships, and monitoring local market/technology trends that inform Astera Labs' strategy

• Cable/Module Manufacturer Enablement:

  • Support China-based cable and module manufacturers who are building AEC/SCM products using Astera Labs silicon under license or partnership agreements

  • Provide design guidance and technical support to manufacturing partners developing their own AEC/SCM product designs incorporating Astera Labs retimer silicon

  • Conduct design reviews and qualification support for partner-designed AEC/SCM products to ensure they meet Astera Labs' performance, quality, and interoperability standards

  • Build the Astera Labs ecosystem of qualified cable/module manufacturing partners in China

Design for Manufacturing (DFM) Excellence

• Leverage Shanghai proximity to cable assembly and module CMs to drive manufacturing-aware design practices:

  • Conduct regular on-site DFM reviews with contract manufacturers during design phases — validating assembly sequence feasibility, process capability alignment, and test access provisions

  • Optimize designs for specific CM process capabilities — considering SMT placement accuracy, reflow profiles, flex handling constraints, overmolding tooling, and automated optical inspection coverage

  • Design AEC/SCM products with explicit consideration for yield-critical process steps — minimizing sensitivity to manufacturing variation while maintaining electrical/mechanical performance

  • Establish rapid prototyping workflows leveraging CM proximity — enabling fast-turn builds, early process learning, and iterative design refinement

• Partner with Manufacturing Engineering and NPI teams to ensure smooth design-to-production transitions with minimal yield loss or production holds

• Participate in CM process development activities — providing design expertise for new manufacturing technologies

Validation & Qualification

• Define and execute hardware validation strategies for AEC and SCM products — covering:

  • Electrical performance: high-speed link testing (BER, eye diagrams, S-parameters), power delivery characterization, jitter/noise analysis

  • Mechanical durability: connector mating cycle testing, cable flex/bend testing, pull strength, strain relief verification

  • Environmental reliability: thermal cycling, humidity exposure, vibration, mechanical shock

  • Standards compliance: form factor dimensional verification, safety certification prerequisites

• Drive a rigorous prototype-to-production validation flow with clear stage gates

• Establish validation infrastructure in Shanghai that enables the majority of AEC/SCM validation activities to be executed locally with high throughput

• Lead failure analysis for prototype and production issues — driving root cause identification and corrective design actions

• Support customer-specific qualification requirements for hyperscale deployments

Technology Development & Next-Generation Design

• Drive next-generation AEC/SCM technology development aligned with silicon and market roadmaps:

  • 224G/lane (1.6T aggregate) AEC/SCM designs with next-generation retimer silicon

  • Advanced substrate/flex technologies for improved loss, density, and thermal performance

  • Novel connector interfaces and cable constructions for future form factors

  • Miniaturization and power density improvements for next-generation module architectures

  • Enhanced smart/managed features and diagnostic capabilities for future SCM products

• Evaluate emerging materials, manufacturing processes, and packaging technologies for AEC/SCM applicability

• Build relationships with substrate vendors, cable suppliers, connector manufacturers, and material suppliers in the China/Asia ecosystem

• Contribute to competitive analysis and technology benchmarking — including monitoring China-based competitors and local technology developments

Cross-Functional Collaboration

• With Santa Clara & Taiwan:

  • Maintain tight alignment with the Senior Director of Hardware Design Engineering on technology roadmap, design standards, resource priorities, and product portfolio decisions

  • Collaborate with the Taiwan design center on shared customer engagement strategies (delineating China vs. broader Asia customer coverage), evaluation platform requirements, and rack-scale integration needs

  • Partner with Signal Integrity engineering on channel modeling, simulation reviews, and design rule development

  • Coordinate with Firmware Engineering on AEC/SCM hardware-firmware co-design — including retimer configuration, CMIS interface implementation, thermal management algorithms, and diagnostic features

  • Participate in global design reviews, architecture discussions, and technology planning sessions

  • Share customer insights, design challenges, and China market intelligence with global product and engineering leadership

• With Manufacturing & Supply Chain:

  • Serve as the primary design engineering interface with AEC/SCM contract manufacturers in China — leveraging proximity for high-cadence engagement during NPI and production ramp

  • Participate in CM selection, qualification, and capability assessment activities for new AEC/SCM product introductions

  • Collaborate with Supply Chain on component sourcing, alternate material qualification, and supplier development for AEC/SCM-specific materials

  • Support Manufacturing Engineering on yield improvement initiatives — providing design expertise for process optimization and defect reduction

• With Sales, FAE & Product Management:

  • Partner with the China Sales and FAE organization to align customer engineering support priorities with revenue targets and strategic account plans

  • Provide technical input for customer proposals, RFQ responses, and competitive evaluations in the China market

  • Represent hardware engineering in customer-facing executive discussions and technical reviews

  • Feed China customer requirements and market feedback into global product roadmap planning

Lab Infrastructure (Shanghai)

• Define and build the Shanghai lab environment to support both AEC/SCM design and customer support activities:

  • High-speed electrical characterization (high-bandwidth oscilloscopes, BER testers, VNAs, TDR systems)

  • Power delivery measurement and characterization

  • Mechanical testing (connector mating fixtures, pull testers, bend/flex test equipment)

  • Environmental/reliability capability (thermal chambers, humidity chambers) or established access to third-party test labs

  • Prototype assembly and rework capabilities for rapid design iteration

  • Failure analysis equipment (microscopy, cross-section, X-ray)

  • Customer demonstration and interoperability test environment — enabling on-site demonstrations, joint testing sessions, and proof-of-concept validation for China customers

  • Customer debug stations — equipped for customer issue replication, root-cause analysis, and solution verification

• Drive capital equipment planning and procurement for the Shanghai lab

• Ensure measurement correlation between Shanghai and Santa Clara labs to maintain data integrity across sites

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, or related technical discipline

• 15+ years of progressive experience in hardware design engineering for high-speed interconnect products — including significant experience with cable assemblies, active cables, optical transceivers, pluggable modules, or high-speed connector/module products

• 5+ years in engineering management/leadership roles, including building and leading multidisciplinary hardware design teams

• Deep technical expertise in high-speed flex circuit, rigid-flex, or substrate design at 56G/112G PAM4 data rates or above

• Strong background in mechanical design for cable module or pluggable transceiver products — including connector interfaces, housings, thermal solutions, and cable strain relief

• Proven track record designing products through full lifecycle — from architecture through qualification and volume production — for high-speed serial link products

• Demonstrated experience in customer-facing technical roles — including design reviews, customer support, applications engineering, or technical account management for semiconductor or interconnect products

• Demonstrated experience working closely with contract manufacturers in China on cable assembly or module manufacturing

• Experience with hardware validation and qualification programs for high-reliability interconnect products

• Strong understanding of manufacturing processes for cable/module products — including SMT, cable termination, overmolding, and automated assembly

• Ability to build engineering teams and establish new engineering site operations

• Native or fluent Mandarin Chinese — required for daily customer engagement, CM collaboration, team leadership, and ecosystem development in China

• Professional proficiency in English — required for daily communication with global engineering leadership, cross-site collaboration, and documentation

• Based in Shanghai with willingness to travel to customer sites and CM facilities across China (30-40%) and to US/Taiwan offices periodically

Preferred Qualifications

• Master's or Ph.D. in Electrical Engineering with emphasis on high-speed interconnects, signal integrity, or electronic packaging

• Direct experience designing Active Electrical Cables (AEC), Active Copper Cables, or Smart Cable Modules incorporating retimer/re-driver silicon

• Experience designing products at 224G/lane (1.6T aggregate) data rates or involvement in next-generation interconnect technology development

• Experience with optical transceiver module design (OSFP, QSFP-DD, QSFP28) — mechanical, electrical, and thermal aspects

• Deep familiarity with relevant form factor specifications: SFF-TA (OSFP, QSFP-DD), CMIS, SFF-8636

• Experience with relevant signal integrity standards: IEEE 802.3ck/dj, OIF CEI-112G/224G

• Track record of successful customer engineering support in China — helping local OEMs, cloud providers, or system integrators achieve design success with semiconductor or interconnect products

• Established relationships with China-based hyperscale customers (Alibaba/Alibaba Cloud, Tencent, ByteDance/Volcengine, Baidu, Huawei, or equivalent) or major China server/switch OEMs (Inspur, H3C, ZTE, Ruijie, or equivalent)

• Track record delivering cable/module products to hyperscale customers for AI/ML infrastructure applications

• Experience at a leading active cable, optical transceiver, or high-speed interconnect company (e.g., Luxshare, Bizlink, Hisense Broadband, Eoptolink, Innolight, Credo, or equivalent)

• Background in retimer/re-driver ASIC integration into cable module products

• Experience with flex circuit design tools and rigid-flex PCB technologies

• Knowledge of cable construction engineering — conductor materials, dielectric properties, shielding techniques, and mechanical performance optimization

• Experience establishing and scaling engineering operations in China for multinational semiconductor or interconnect companies

• Familiarity with EDA tools (Cadence Allegro/OrCAD, Ansys HFSS/SIwave, Keysight ADS, SolidWorks/Creo)

• Understanding of China-specific regulatory, compliance, or procurement requirements for data center infrastructure products

• Experience navigating technical engagement with both Chinese state-owned enterprises and private technology companies

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.