Director Post-Si Electrical Validation Engineering

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs is seeking a Director of Post-Si Electrical Validation Engineering to lead the development, bring-up, and validation of ASIC SerDes and PCIe PHY products that enable rack-scale AI infrastructure. Working closely with ASIC, systems, firmware, signal integrity, power integrity, mechanical, thermal, manufacturing, and customer engineering teams, you will guide products from concept and architecture through qualification and mass production. 

This is a hands-on leadership role in a fast-moving environment. You will lead a talented engineering team while stepping in to solve complex technical problems, engage directly with customers, and improve hardware development processes. Your work will help ensure Astera Labs’ connectivity and memory products deliver reliable, high-performance systems for cloud service providers, server manufacturers, and networking OEMs. 

Key Responsibilities 

• Board Product Strategy and Technical Leadership 

• • Lead ASIC Electrical-level (PHY) validation strategy across product definition, architecture, PCB/test fixture development, Validation Automation, data review, bring-up, debug, optimization, qualification, and production release. 

• • Define validation plans, coverage goals, risk assessments, schedules, and exit criteria for high-speed ASIC and PHY IP 

• • Make hands-on technical contributions to unblock critical design, validation, and customer issues in a dynamic, fast-paced environment. 

• High-Speed SerDes Validation 

• • Direct ASIC Power-On and bring-up, silicon/PCB debug, PVT characterization, margin analysis, and performance optimization across voltage, temperature, channel, and workload conditions. 

• • Validate high-speed NRZ and PAM4 SerDes-based protocols, including PCIe Gen 3 and above 

• • Apply signal/power integrity, SerDes/PHY knowledge, coding, and lab expertise to identify risks and drive practical solutions across circuits, power distribution, connectors, sockets, and cables. 

• Cross-Functional and Customer Execution 

• • Partner with ASIC, system validation, firmware, systems, mechanical, thermal, quality, compliance, manufacturing, and customer engineering teams to deliver robust products. 

• • Engage key internal customers to understand system requirements, evaluate form factors, propose complete board solutions, and resolve issues through production support. 

• • Collaborate with external vendors for test equipment, bench sockets, temperature forcing units, RF cables, PCB vendors, and related suppliers to ensure validation platforms are automated, robust, and scalable. 

• Team Development and Productization 

• • Build, mentor, and develop a high-performing engineering team while establishing clear ownership, technical standards, and execution mechanisms. 

• • Drive products from concept to mass production, including validation data reviews, code/automatin reviews, validation reporting, documentation, and post-production support. 

• • Improve post-Silicon development processes and methodologies, share lessons learned, and reuse validation best practices across Astera Labs’ connectivity and memory product portfolio. 

Basic Qualifications 

• Bachelor’s degree in Electrical Engineering or a related technical field. Master’s degree in Electrical Engineering preferred. 

• 12 - 15+ years of relevant experience, consistent with Astera Labs’ standardized Director level. 

• Technical management experience leading design, validation, product, or system engineering teams. 

• Experience with high-speed serdes PHY Validation over PVT conditions and taking products from concept to validation plan, validation, production release and post-production support.  

• Strong background in high-speed SerDes IP validation and PHY tuning, signal/power integrity, and automation using common lab equipment such as high-speed oscilloscopes, BERTs, and VNAs 

• Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! 

• Strong cross-functional collaboration, technical communication, prioritization, and independent problem-solving skills. 

Preferred Qualifications. 

• Experience leading SoC Debug and development for high-speed interfaces such as PCIe5, PCIe6 or PAM4 802.3 Ethernet. 

• Working knowledge of key, high-speed PHY design blocks such as PLL’s, DFE, Tx EQ,FFE, CDR, etc and signaling concepts such as PAM4 

• Strong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaboration 

• Deep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis. 

• Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA 

• Startup experience and a proactive, hands-on, customer-focused approach to solving complex problems. 

Salary range is $210,000 to $275,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.