RTL Design Engineer
About Celestial AI
As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.
The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.
This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.
Job Description:
As an RTL design engineer, you will collaborate with architects and implementation leads to define and implement RTL modules as required. Emphasis will be placed on minimizing power consumption while creating high quality, re-useable design.
ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Design and implement custom RTL modules for the Celestial SoC
- Author detailed design specification documents
- Collaborate with DV engineers on test requirements to ensure bug free designs
- Evaluate performance, area, and power tradeoffs
- Drive coverage closure for your designs
QUALIFICATIONS:
- 3 or more years logic design experience
- RTL design experience with SystemVerilog; familiarity with SVA
- Understanding of low power design techniques
- Knowledge of / Experience in Network Protocols
- Experience designing state machines, data paths, arbiters, and clock domain crossings
- Working knowledge of RTL quality assurance tools (Lint, CDC) and LEC preferred
- Proficient with scripting languages and task automation
- BS plus 3 years relevant experience. MS preferred
Location: San Francisco Bay Area or Orange County, CA
For California location:
As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $135,000.00 - $155,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.
We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.
Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.
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