Senior ASIC/VLSI Synthesis and Design Engineer

About Celestial AI

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

ABOUT THE ROLE

We are looking for a Senior ASIC/VLSI Synthesis and Design Engineer to drive the development of high-performance, low-power digital designs for cutting-edge ASICs and SoCs. This role involves optimizing power, performance, and area while ensuring timing closure, gate-level simulation, and post-silicon validation. You will collaborate with cross-functional teams to implement synthesis methodologies, constraint development, DFT integration, and power analysis.

If you have a strong background in ASIC/VLSI design, with deep expertise in synthesis, timing closure, DFT, and post-silicon debug, we want to hear from you.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Develop and implement synthesis flows for high-performance, low-power digital designs using industry-standard EDA tools (Genus, Tempus, DC, PrimeTime, Conformal LEC, etc.).
• Define and implement synthesis constraints at block and top levels, ensuring optimal timing closure and gate-level simulation.
• Optimize clock distribution, pipelining, and register balancing for maximum performance.
• Perform Logical Equivalency Checks at all design stages.
• Work closely with DFT teams to integrate scan chains, ATPG, and MBIST into the synthesis flow.
• Perform power analysis and optimization, applying techniques like power gating, clock gating, voltage scaling, and dynamic voltage frequency scaling.
• Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs.
• Collaborate with physical design teams to ensure smooth handoff and timing closure through optimizations, analysis, physical synthesis and ECO implementation as needed.
• Lead design methodology improvements, driving efficiency in RTL-to-GDSII flows.
• Drive post-silicon validation and debug, ensuring successful production ramp-up.

QUALIFICATIONS

• Bachelor’s degree with 8+ years of experience, or Master’s degree with 6+ years of experience in Computer Science, Electrical Engineering, Information Technology or a related technical field.
• 8+ years of ASIC/VLSI design experience, focusing on synthesis and timing closure for large scale design in deep submicron technology.
• Expertise in Verilog/SystemVerilog RTL coding and constraint development for synthesis.
• Proficiency in synthesis tools from leading EDA vendors (Cadence, Synopsys, Mentor).
• Experience with gate-level simulation, static timing analysis (STA), and power-aware synthesis.
• Strong post-silicon debug and validation skills, including production bring-up and failure analysis.
• Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow optimization.
• Strong problem-solving, debugging, and collaboration skills in a fast-paced environment.

LOCATION: Orange County, CA, or Santa Clara, CA

For California Location:

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews. 

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.

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