MTS SoC Design Verification Engineer

CScale is building the interconnect for gigawatt-scale AI. As AI scale-up moves toward deployments spanning thousands of accelerators and dozens of racks, the network needs to deliver high bandwidth, predictable low latency, and continuous communication. CScale is building integrated optical interconnect designed for this new scale, enabling accelerators to work together like a single, much larger computer. But at this scale, performance is only part of the challenge. Optical failures are inevitable, and the system needs to keep running. CScale is designing the interconnect for continuity. Lasers will fail. Compute shouldn’t. The ambition is simple: Build AI interconnect you can take for granted. CScale came out of stealth in September 2026 with $145 million in Series C funding, bringing total funding to $188 million.

SoC Verification – MTS SoC DV Engineer 
Experience: 8–10 Years 

Role Summary 

This role serves as the hands-on technical lead for SoC Verifications. The position drives testbench architecture, scalable and reusable verification strategies, testbench development, verification sign-off, documentation, and team mentoring. Key responsibilities include functional and data path verification. The role ensures comprehensive verification sign-off and delivers a robust, high-quality, and reusable verification environment aligned with project objectives. 

Key Responsibilities 

• Define and drive verification strategy across sub-system and SoC-level domains. 
• Develop verification environment from the scratch for complex SoC leveraging both C-based and UVM methodologies  
• Develop and manage comprehensive test plans and coverage models. 
• Collaborate with design teams to define system boot, reset sequence, and design configuration for various use-cases. 
• Collaborate with design team to define debug architecture and debug/trace verification.
• Manage project milestones, deliverables, schedules, and cross-functional dependencies.
• Lead waveform and code review with team members and own technical documentation. 
• Mentor and grow teams of DV engineers, including external contractors.
• Take full ownership of verification and final sign-off, following multiple review cycles that encompass functional correctness, power analysis, performance validation, gate-level simulations, and comprehensive coverage closure
• Support firmware/software bring-up and post-silicon debug. 

Required Skills 

• Strong hands-on experience in System Verilog and UVM methodology.  
•  Solid understanding of SoC TB architecture and test-plan creation
• Expertise in power-aware verification, including UPF-based methodologies and gate-level simulation. 
• Experience in DV sign-off flows, rigorous checklist-based tracking to ensure completeness      
• Strong debug skills across RTL, integration, and HW–SW interaction.  

Added Advantage 

• Python/TCL scripting experience and post-silicon bring-up 
• Performance modeling and benchmarking.