Silicon Photonics Design Engineer

Cspeed IO is a stealth start up backed by Sutter Hills Ventures and Atreides Capital - headquartered in Palo Alto, CA.  Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.

Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures.  Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.

Silicon photonic integrated circuits are at the heart of our optical system, and the device designs produced in this role directly determine what we can deliver at scale. We are seeking a Silicon Photonics Design Engineer to own the design and validation of silicon photonic devices and circuits from concept through silicon — working in a small, cross-functional team where individual contributions are highly visible and directly shape product outcomes. The right candidate brings strong integrated photonics fundamentals, hands-on simulation and layout experience, and the instinct to design for manufacturability, not just peak performance.

Responsibilities

• Design silicon photonic devices and PIC building blocks — including passive and active components such as waveguides, interferometers, resonators, couplers, modulators, and photodetectors — with explicit consideration of process variation and production yield.
• Perform optical and electro-optic simulations to optimize device performance; conduct tolerance analysis and process corner studies to ensure robust operation across fabrication variations.
• Implement designs using commercial silicon photonics PDKs and foundry design rules; evaluate process sensitivities and ensure designs meet manufacturing constraints.
• Define design-of-experiments (DOE) strategies and design test structures and test chips to validate device concepts, characterize process sensitivities, and close the loop between simulation and silicon results.
• Generate PIC layouts and prepare GDS for fabrication; support design verification and tape-out of photonic circuits.
• Analyze measurement data from fabricated devices and correlate results with simulations to guide iterative design improvements.
• Work closely with electronics, packaging, and systems engineers to integrate PIC solutions into broader hardware platforms.

Required Qualifications

• Strong foundation in integrated photonics and optical device physics, with hands-on experience designing passive and active silicon photonic components.
• Proficiency with photonic simulation tools — FDTD, eigenmode solvers, and circuit-level simulation (e.g., Ansys Lumerical, Photon Design, or equivalent).
• Demonstrated experience with PDK-based design flows and photonic layout tools for GDS generation (e.g., Cadence, KLayout, Luceda IPKISS, or similar).
• Experience designing photonic test chips and executing design-of-experiments to validate device concepts and process sensitivities.
• Programming proficiency in Python or MATLAB for simulation automation, data analysis, and statistical evaluation of device performance.

Preferred Qualifications

• 3 or more years of relevant industry experience in silicon photonics design.
• Ownership of photonic designs from concept through silicon validation — including tape-out, characterization, and design iteration.
• Hands-on experience with photonic device characterization and optical measurement setups.
• Experience integrating photonic components into larger PIC designs or multi-function circuits.

Education

Ph.D. in Electrical Engineering, Photonics, Applied Physics, or a closely related discipline with demonstrated research focus in integrated photonics or silicon photonic device design. Candidates with relevant industry experience in lieu of a Ph.D. will be considered based on the depth and scope of their design and tape-out record.