InnoPhase Inc., DBA GreenWave™ Radios and Synergic Emergence have a co-employment relationship. For over three years, GreenWave Radios has partnered with Synergic Emergence, a professional employment organization provider, to offer our employees the best benefits and services. This arrangement means that Synergic Emergence provides employee pay checks and benefits, and GreenWave Radios will provide employment, evaluation, and advancement. By outsourcing some HR functions, GreenWave Radios can focus on what we do best – developing and implementing highly innovative SOC cellular radio integrated circuit products.
Job Description
InnoPhase Inc., DBA GreenWave™ Radios Bangalore is looking for a Tech Lead - Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products. This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!
Key Responsibilities
•Master’s and/or bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS.
•10 or more years of relevant experience across multiple verification environments for IPs, Sub-systems, and SoCs.
•Proficient in SystemVerilog, UVM, Verilog/VHDL; scripting languages (Python, Perl, Tcl/Shell etc.) and experience with Bare-Metal C Program.
• Expertise in developing UVM testbench environment and components (Monitor, Scoreboard, Driver, Agent etc), SystemVerilog Assertions (SVAs) and Functional Coverage.
• Proficient with ARM Processors (Cortex) based SoC verification, multi-processor Cache Coherency and Memory/DMA controllers.
• Strong working knowledge on bus/ interconnect protocols like AMBA – AXI/AHB/APB, PCIe, USB, Ethernet etc.
• Experience with industry-standard interfaces (PIPE, SerDes etc.) and peripheral protocols – QSPI, SPI, UART, I2C etc.
•Hands-on experience with integration of VIPs/UVCs (Cadence/ Synopsys) and C-reference models into multiple UVM testbench environments.
•Experience in Cadence – Design, Simulation & Debug Tools/ Environments and vManager for DV metrics extraction and regression.
•Track record of successfully executing block or chip-level verification strategy & plans.
•Excellent communication and presentation skills, energetic and self-motivated.
•Work effectively with an off-site/ offshore design and verification teams across locations.
Job Requirements
• Master's and/or Bachelor’s degree in engineering (or equivalent) in EC/ EE/ CS.
• Hands-on experiences using Cadence AMBA BFM and VIP with DV sequences and bare-metal C code.
• Experiences in Cadence vManager for DV metrics extraction and regression • Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch.
• Proficient in SystemVerilog, Verilog/VHDL, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.
• Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based test bench environments, writing SystemVerilog Assertions (SVAs), with embedded software design and testing.
• Strong knowledge about multiple testbench architectures, industry-standard interfaces/ protocols (AXI, AHB, APB, , PCIe, PIPE interface, Serdes, UART, SPI, I2C, QSPI, DMA etc).
• Experience in Cadence Design Tools/ Environments and exposure to Cadence VIPs/ UVCs is plus.
• Track record of successfully executing block or chip-level verification plans.
• Excellent communication and presentation skills, energetic and self-motivated.
• Work effectively with an off-site/ offshore design and verification teams across locations.
Benefits
• Competitive salary and stock options.
• Learning and development opportunities.
• Employer paid health Insurance.
• Earned, Casual, Sick & parental leaves.
