Principal Engineer, DTCO

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What You’ll Do

We are looking for experienced technologists who will independently research and explore future logic technology paths, capabilities, and applications through design/system-technology optimization (DTCO).

The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose.  He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes.  The candidate should have demonstrated skills and experience in standard cell architecture creation, logic cell library characterizations Place and Route, Process Design Kit (PDK) generation, and a strong understanding of Logic process integration. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.

Location: This is a Hybrid role, working onsite at our San Jose headquarters at least 3 days per week with the flexibility to work remotely the remainder of your time.

Job ID: 42367

Reports to: Senior Director

• Create and optimize standard cell architecture and libraries to enable new device scheme and technology Performance, Power, Area, Cost (PPAC) assessment. 
• Optimize DTCO collaterals to enable block-level design.
• Analyze technology design rules and process capabilities, and identify their impact on PPAC.
• Develop early DTCO methodologies to assess new technology options.
• Develop internal benchmarking capability based on available data, modeling, and/or learning from external sources, and create assessments to share with internal R&D teams.
• Collaborate and guide external vendors on DTCO development.

What You Bring

• PhD in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science and Engineering, Computer Science, Physics or related fields and 15+ years of industry experience.
• Standard cell layout design and library generation skills.
• RTL synthesis, place and route, and timing analysis skills.
• DTCO modeling skills, from the logic standard cell to process design kit (PDK), including Library/Technology/Design Rule Check deck generation.
• SRAM bit-cell design and macro simulation skills is a strong plus.
• Understanding of power delivery network schemes.
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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