Senior Staff Engineer, ASIC Design

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Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Do

Platform Solutions (PS) is part of Samsung Semiconductor, Inc. (SSI), the industry’s technology and volume leader in semiconductor products. Platform solutions team belongs to Samsung Foundry in SSI. PS team’s mission is to create solutions that can synergize for revenue increase across the divisions in Samsung. One of the solutions we are working on is to develop a design platform for customized HBM product.

We are looking for ASIC designer for customized HBM Buffer Die Design to join our team in San Jose, CA. A successful candidate will be responsible for creating and deploying HBM buffer die design solution for next generation of customized HBM products working with multiple engineering teams.

Location: Daily onsite presence at our San Jose Headquarters in alignment with our Flexible Work policy

Reports to: Senior Director, Solution Planning

You will collaborate with architects, ASIC front-end and Design Verification teams to understand buffer die architecture, implement and get it verified.

• Architecting and RTL design for customized HBM buffer die
• Link layer design for utilizing UCIe IPs (between HBM memory controller and UCIe IPs)
• Design and implementation of NoC, and verification
• Interface design for maximizing bandwidth between HBM memory and logic die
• Low power design (Clock and power management), generating a UPF file and verification through multi-voltage simulations
• Scope out third-party IP requirements and solicit vendors
• Perform LINT and CDC checks
• Static Timing analysis including generating constraints
• Understanding of DFT strategies, streaming scan fabric, IEEE protocols
• Experience of synthesis, DFT, functional verification, UVM verification

What You Bring

• Bachelors in Electrical Engineering, related degree with 15+ years of experience or Masters in Electrical Engineering, Business, or comparable engineering degree with 13+ Years of Industry Experience Preferred.
• 3+ years of ASIC Design Experience.
• Experience in designing data transfer/packetizing format
• Experience in Verilog/System Verilog programming skills.
• Experience in interactive and waveform debug skills.
• Experience with low-power design and clock domain crossings.
• Design/verification experience of link layer for utilizing UCIe Ips
• Design/verification experience of data path protocol (packetizing, error correction and etc.)
• Design/verification experience of ARM Cortex system using different types of BUS.
• Firmware design and debugging experience
• Experience with scripting such as (Python, Perl, TCL, Shell programming)
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

#LI-MD1

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When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

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