Senior Staff, Serdes DSP Design

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Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. 

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams.

Location:  Daily onsite presence at our San Jose, CA  headquarters in alignment with our Flexible Work policy

What You’ll Do

This team is focused on digital DSP design for high speed Serdes. Ideal candidates would have 10+ years of industrial experience specialized in SerDes DSP and digital/logical PHY design. Candidates are expected to have a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with system and analog team. 

What You Bring

• Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhDs with 10+ years of experience in high speed Serdes DSP design.
• Proficient with Verilog-HDL/System Verilog coding for PAM4/PAM6 DSP based SerDes including link-training, analog circuits and ADC foreground/background calibration and adaptation.
• Deep understanding of high-speed serial interconnect architectures such as PCIe, 100/200Gbps per lane ethernet and design trade-offs  
• RTL logic design, debug and functional verification
• Experience in synthesis, CDC, static timing analysis.
• Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow.
• Deep understanding of Signal Integrity and Power Integrity modeling for High Speed designs.
• Understanding of micro architecture with standard peripherals such as AMBA BUS, I2C, SPI and UART.
• Understanding of design for testability (DFT) flow.
• Strong background in DSP and algorithms is a plus.
• Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus.
• Understanding of fundamental physical design flows and stages
• Firmware development of embedded microcontroller systems is a plus
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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