Process Assembly Design Kit (PADK) Development

Job Title: Process Assembly Design (PADK) Development 
Office Location: San Jose, CA
Work Model: Onsite
      

About SK hynix America

At SK hynix America, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix America, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Responsibilities:

• Define, Develop and maintain the PADK for advanced IC packages involving heterogenous integration using chiplets.
• Collate input data requirements to build an initial comprehensive PADK by researching standard advanced packaging requirements and evolving them overtime for future looking novel technologies.
• Work closely & absorb customer feedback to improvise baseline PADK feature-set gaps and devise strategies to implement those features via lifecycle iterations.
• Develop process flow for initial setup of advanced package architecture involving input of design collaterals, advanced packaging assembly rules, chiplet features and standards, thermal and electrical performance constraints, and DFM/DFR/DFT constraints.
• Define and develop execution flow for performing LVS checks on interposers, substrates and bridge die to ascertain error free netlist and layout connectivity at intermediate design checkpoints and final tapeout signoffs.
• Work with customers and vendors to understand and implement comprehensive design rule checking capability and drive automation activities to setup DRC routines.
• Strategize efforts to minimize the PADK setup and DRC reporting time and effort by understanding baseline flow bottlenecks and coworking with EDA vendors to drive tool feature improvements and automation.
• Closely work with stakeholders (including but not limited to substrate designers, interposer designers, assembly engineers and customers ) to ensure end to end requirements and features are appropriately absorbed into the PADK.
• Act as a focal point between EDA vendors, designers and customers to validate and obtain sign-off of the entire PADK flow before releasing major and minor versions of updated kits.
• Drive strategic R&D PADK & related projects, develop advanced package design kits
• Keep in sync with ongoing industry innovations in technologies to understand impacts to advanced package architecture, design and simulation methodology and manufacturing innovations that directly affect PADK capabilities.

Minimum Qualifications:      

• MS in Electrical/Mechanical Engineering or equivalent industry experience
• 5+ years of experience in organic substrate design including design database setup, constraint setup, physical verification flow, DRC checking & automation
• Familiarity with conventional and advanced packaging design flows (2.5D, CoWoS, SOIC, 3D), basic understanding of SI/PI concepts and thermal/mechanical constraints
• Working knowledge in DRC (design rule check), LVS (Layout versus schematic), and physical design layout tools
• Effective communication skills
• Experience working effectively with cross-functional teams  

Preferred Qualifications:     

• PhD in Electrical/Mechanical Engineering or equivalent industry experience
• 7+ years of experience in advanced packaging architecture, design and automation, physical verification flows and methodologies for silicon nodes
• Hands on experience in CAD-like roles to evaluate tools, flows and tech files to be able to evaluate and select best path forward
• Working knowledge in DRC (design rule check) & LVS (Layout versus schematic) flows and physical design layout tools
• Working knowledge on advanced package design architectures and signal & power integrity implications
• Experience working closely with EDA partners for developing and evolving CAD tools & features to enable feature implementation or improvisation.
• Effective communication skills to absorb customer requirements and relay back enhancements for tool and flow enhancements.
• Experience working effectively with cross-functional teams

Benefits:       

• Top Tier health insurance at no employee cost
• Paid day offs: PTO + Company Holidays + Happy Fridays
• Paid Parental Leave Program
• 401k Matching
• Educational reimbursement up to $10,000 per year
• Donation Matching and volunteering opportunities
• Corporate discount programs
• Free Breakfast/Lunch/Dinner provided to employees

Equal Employment Opportunity:

SKHYA is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws. 

Compensation: