Engineering - Hardware / AI Hardware
Job
Performance Architect, AI HW
Toronto, Ontario, Canada
Power Architect
Risc-V Architect
Silicon Lead, Automotive/Robotics
Staff Design Verification Engineer, AI HW
Engineering - Hardware
Fabric SOC Architect
United States
High-Performance Computing Architect
Memory Architect
North America
Networking ASIC Architect
Power Architect, AI Data Center Chiplets
Power Architect, Automotive Chiplets
Project Administrator
Tokyo, Japan
Sr. Staff, Digital Design Verification Engineer, Chiplets
新北市, New Taipei City, Taiwan
Staff Engineer, RTL Design, Chiplet
Verification Engineer
Japan
Engineering - Hardware / Architecture
Architecture, Technical Program Manager
Automotive and Robotics SOC Architect
Machine Learning SoC architect
Robotics SOC Architect
SOC Architect - Automotive
RISC-V CPU Microarchitecture / RTL
Chiplet Verification Architect
CPU Design Verification Engineer
Formal Verification Lead
Ai Kernel Development Architect
Santa Clara, California, United States
CPU Architect, Load-Store
CPU Workload Performance Analysis Engineer
Heterogeneous SoC Simulation Architect
Java Performance Optimization Engineer
Midcore CPU Performance Architect
Staff Technical Program Manager, Physical Design
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Technical Program Manager, RISC-V IP
Engineering - Hardware / Physical Engineering
Sr. Analog/Mixed-Signal Architect
Santa Clara, California, United States; United States
Sr. Technical Program Manager, Packaging
Toronto, Ontario, Canada; 新北市, New Taipei City, Taiwan
Foundry Technologist Engineer
Physical Design Engineer - Power Grid/EMIR
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States; United States
Physical Design Engineer - STA
Senior Physical Design Engineer
SoC Physical Design Verification Engineer
SoC Top-Level Physical Design Engineer
Sr. Staff CPU Physical Design Lead
Staff Engineer Power Analysis
Staff Physical Design Engineer – EMIR
Austin, Texas, United States; Santa Clara, California, United States
CPU Core Design Verification Engineer - Contractor
Customer TPM, RISCV
Austin, Texas, United States
Director, RISC-V Software Ecosystem
Principal Engineer, CPU System Microarchitect
Sr Staff CPU Core/Unit Verification Engineer, Functional Safety
Sr. Staff, Design Verification - CPU Cluster SoC
Sr.Staff, Design Verification - CPU Cluster / SoC
Bengaluru, Karnataka, India
