Job
Field Application Engineer, AI Systems & Solutions
Austin, Texas, United States; Santa Clara, California, United States
Customer
Design Verification Engineer, Automotive Robotics New
Munich, Germany
Emulation Engineer, Automotive Robotics New
Field Application Engineer, Automotive RoboticsNew
Functional Safety Hardware Engineer, Automotive RoboticsNew
Munich Site Manager New
RTL Engineer, Automotive RoboticsNew
SOC Architect New
Software Architect, Automotive Robotics New
Technical Writer, Automotive Robotics New
Test Engineer, Automotive RoboticsNew
Engineering - Hardware / AI Hardware
Performance Architect, AI HW
Toronto, Ontario, Canada
Power Architect
Risc-V Architect
Senior Design Verification Engineer, AI HW
Engineering - Hardware
ASIC Networking Engineer
United States
Chiplet Physical Design Engineer
Fabric SOC Architect
High-Performance Computing Architect
Memory Architect
North America
Power Architect, AI Data Center Chiplets
Project Administrator
Tokyo, Japan
RISC-V AI / HPC & Agentic Software Engineering Lead
Senior DFT Engineer, Architecture
Japan
Verification Engineer
Engineering - Hardware / Architecture
Automotive and Robotics SOC Architect
RISC-V CPU Microarchitecture / RTL
CPU Design Verification Technical Lead
Formal Verification Engineer
CPU Architect, Load-Store
Staff Technical Program Manager, Physical Design
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Technical Program Manager, RISC-V IP
Engineering - Hardware / Physical Engineering
Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
Silicon Validation Engineer
Santa Clara, California, United States
Staff Analog Design Engineer
Package Design Engineer
Toronto, Ontario, Canada; 新北市, New Taipei City, Taiwan
Physical Design Engineer - Power Grid/EMIR
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States; United States
Physical Design Engineer - STA
Physical Design Flow Engineer
Senior Physical Design Engineer
SoC Physical Design Verification Engineer
SoC Top-Level Physical Design Engineer
Staff Physical Design Engineer – EMIR
Static Timing Analysis (STA) Methodology EngineerNew
Director, RISC-V Software Ecosystem
Sr.Staff, Design Verification - CPU Cluster / SoC
Bengaluru, Karnataka, India
Sr. Staff Engineer, Automotive System Software
Sr Staff Engineer, CPU System Microarchitect
Austin, Texas, United States
Sr Staff Engineer, CPU System MicroarchitectNew
Sr. Staff Engineer, Post-Silicon Validation
