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Staff Engineer, ASIC Design Methodology

Boston, Massachusetts, United States; Toronto, Ontario, Canada

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for an ASIC Design Methodology Engineer to advance our design infrastructure and flows across RTL development, verification, and physical implementation. This role is ideal for engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate silicon success.

This role is hybrid, based out of Toronto, Ottawa, Austin, or Boston.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

 

Who You Are

  • A strong advocate for design quality and productivity, with expertise in ASIC design flows.
  • Skilled in RTL design and familiar with static and dynamic analysis tools.
  • Comfortable automating design checks and improving methodology for scalability and reuse.
  • A collaborative engineer who partners effectively across RTL, verification, and backend teams.

 

What We Need

  • Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration.
  • Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies
  • Develop synthesis timing constraints (SDC) and low power design specifications (UPF)
  • Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness.
  • Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime.

What You Will Learn

  • How large-scale AI SoCs are architected, integrated, and brought to silicon.
  • How methodology choices directly impact design performance, power, and verification closure.
  • How to build and scale ASIC design flows supporting cutting-edge compute architectures.
  • How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams.

 

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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