Job
AI/ML Physical Design Flow Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Full-Chip Physical Design Verification Engineer
Physical Design Engineer, ML4PD
Physical Design Engineer, PnR
Physical Design Engineer - STA
Staff Engineer, Physical Design
Top Level Physical Design Engineer
Advanced Physical Design
Physical Design Engineer, Timing
Design Verification Lead, AI Hardware
Toronto, Ontario, Canada
Director, Customer Hardware Engineering
Staff Design Verification Engineer, AI HW
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada; Zürich, Switzerland
AI Hardware
Physical Design Engineer, AI Accelerator IP
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada
Physical Design Methodology Engineer, AI HW IP
Senior Embedded Engineer, AI IP
Belgrade, Serbia
Power Architect
Austin, Texas, United States; Boston, Massachusetts, United States; Santa Clara, California, United States; Toronto, Ontario, Canada
Principal CPU Microarchitect - RISC-V & AI Compute
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada
C++ Machine Learning Engineer, Models Training
Gdańsk, Pomeranian Voivodeship, Poland; Warszawa, Masovian Voivodeship, Poland
Software Engineer, Acceleration Kernel Development
Santa Clara, California, United States
AI SW
Staff Software Engineer, Cloud Infrastructure
Staff Technical Program Manager, Data Center DeploymentNew
Systems Engineer, Data Center Debug
Machine Learning Engineer, AI Models
Cyprus
Software Engineer-AI Model Bring Up
Tokyo, Japan
Acceleration Kernel Developer Lead
Sr. Engineer, Kernel Development and Optimization
GCC Compiler Engineer
Software Engineer, Scale Out
Software Engineer, TT-Distributed
Software Engineer, TT-Fabric
Technical Program Manager, Product Software
Austin, Texas, United States; Santa Clara, California, United States
Chiplet Physical Design Engineer
DFT Engineer
Fabric SOC Architect
Interconnect and Compute Architect
Physical Design CPU Methodology Engineer
RISC-V AI / HPC & Agentic Software Engineer
新北市, New Taipei City, Taiwan
RISC-V AI / HPC & Agentic Software Engineering Lead
Senior DFT Engineer, Architecture
Technical Program Manager SOC & Digital Design New
Verification Engineer
Japan
Architecture
CPU Microarchitect, Vector and Matrix Compute
Santa Clara, California, United States; Spain
CPU Verification Fellow, RISC-V High-Performance Processor
Formal Verification EngineerNew
Front End Design Verification Engineer
Midcore Design Verification Engineer
Performance Architect, CPU Cluster
Performance Modeling Architect
Technical Program Manager, Architecture
Datacenter & Agentic AI Workload Performance Analysis EngineerNew
Customer - Operations
Business Development Lead(robotics/automotive), APAC
Asia; Japan; Korea; Singapore
