Job
AI/ML Physical Design Flow Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Full-Chip Physical Design Verification Engineer
Physical Design Engineer, PnR
Physical Design Engineer - STA
Top Level Physical Design Engineer
Advanced Physical Design
Physical Design Engineer, ML4PD New
Austin, Texas, United States
Physical Design Engineer, Timing
Design Verification Lead, AI Hardware
Toronto, Ontario, Canada
Director, Customer Hardware Engineering
Senior Design Verification Engineer, AI Hardware
Belgrade, Serbia
Senior Engineer, RTL Design, AI Hardware
Staff Design Verification Engineer, AI Hardware
Staff Design Verification Engineer, AI HW
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada; Zürich, Switzerland
Staff Engineer, RTL Design, AI Hardware
AI Hardware
Physical Design Engineer, AI Accelerator IP
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada
Physical Design Methodology Engineer, AI HW IP
Senior Compiler Engineer, AI IP
Senior Embedded Engineer, AI IP
Sr. Staff Engineer, IP Runtime
Austin, Texas, United States; Toronto, Ontario, Canada
Power Architect
Austin, Texas, United States; Boston, Massachusetts, United States; Santa Clara, California, United States; Toronto, Ontario, Canada
Principal CPU Microarchitect - RISC-V & AI Compute
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada
C++ Machine Learning Engineer, Models Training
Gdańsk, Pomeranian Voivodeship, Poland; Warszawa, Masovian Voivodeship, Poland
Software Engineer, Acceleration Kernel Development
Santa Clara, California, United States; Toronto, Ontario, Canada
AI SW
Staff Technical Program Manager, Data Center Deployment
Systems Engineer, Data Center Debug
Low-Level Software Engineer, LLK
Machine Learning Engineer, AI Models
Cyprus
Software Engineer-AI Model Bring Up
Tokyo, Japan
Sr. Engineer, Kernel Development and Optimization
Technical Program Manager, Platform & Runtime Engineering
Software Engineer, Scale Out
Technical Program Manager, Product Software
Austin, Texas, United States; Santa Clara, California, United States
Chiplet Physical Design Engineer
Santa Clara, California, United States
DFT Engineer
Interconnect and Compute Architect
RISC-V AI / HPC & Agentic Software Engineering Lead
Senior DFT Engineer, Architecture
Technical Program Manager SOC & Digital Design
Verification Engineer
Japan
Architecture
CPU Microarchitect, Vector and Matrix Compute
Santa Clara, California, United States; Spain
CPU Verification Fellow, RISC-V High-Performance Processor
Formal Verification Engineer
Front End Design Verification Engineer
Midcore Design Verification Engineer
Performance Architect, CPU Cluster
Austin, Texas, United States; Santa Clara, California, United States; Santa Clara, California, United States
Performance Modeling Architect
Physical Design CPU Methodology Engineer
Technical Program Manager, Architecture
Datacenter & Agentic AI Workload Performance Analysis Engineer
Datacenter & Agentic AI Workload Performance Optimization Engineer
