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Contract-RISC-V CPU Microarchitecture RTL Engineer

Tokyo, Japan

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

The Graduate RISC-V CPU Microarchitecture / RTL Engineer will play a key role in developing next-generation CPU designs. This position requires a foundational understanding of CPU architecture, RTL, design verification, and physical design flow. The ideal candidate will contribute to unit specification, RTL design, verification strategy, and PPA closure.

This role is hybrid , based out of Tokyo, Japan.

 

Who You Are

  • You have a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • You have a basic understanding of high-performance CPU RTL for x86, Arm, POWER, SPARC, or RISC-V processors.
  • You have foundational knowledge of CPU microarchitecture, design verification strategies, and power, performance, and area trade-offs.
  • You are an analytical problem solver and collaborative communicator who can work effectively across multiple disciplines.

What We Need

  • Contribute to the microarchitecture specification of assigned RISC-V CPU units, such as branch prediction, rename, instruction scheduling, vector execution, load/store, vector load/store support, and memory management units.
  • Design and maintain high-quality RTL using Verilog, SystemVerilog, VHDL, or similar hardware description languages.
  • Support unit verification by reviewing and refining verification environments and applying appropriate simulation, formal, and checker-based methodologies.
  • Contribute to PPA closure and actively use AI tools to accelerate and improve the CPU design process.

What You Will Learn

  • How to develop microarchitecture specifications that address design, verification, and PPA closure from the beginning of the design cycle.
  • How next-generation RISC-V CPU units are designed, verified, optimized, and integrated across architecture, RTL, design verification, and physical design flows.
  • Practical application of RISC-V architecture concepts, including the V-extension and vector execution, in high-performance CPU design.
  • AI-driven design methodologies and tools that improve engineering productivity and design quality.

                                             

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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