Senior Digital Design Engineer-CXL/PCIe

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

Senior Digital Design Engineer - PCIe

We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibilities:

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for PCIe/CXL protocols.
• Ensure timing closure, assess verification completeness
• Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows

Basic Qualifications:

• Bachelor's in Electrical Engineering (Master's preferred).
• 7+ years of digital design experience, with 2+ years focused on high-speed PCIe/CXL implementation.
• Proven expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design, gate-level simulations, and design verification.
• Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Required Expertise:

• Hands-on experience with high-speed protocols like PCIe/CXL (Gen4+).
• Strong proficiency in System Verilog/Verilog and scripting (Python/Perl).
• Experience with block-level and full-chip design at advanced nodes (≤ 16nm).
• Silicon bring-up and post-silicon debug experience.
• Familiarity with Synopsys/Cadence tools and UVM-based design verification.

Preferred Experience:

• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm
• Knowledge of system-level design for Gen4/5/6 PCIe.
• Understanding of PCIe PHY, DFT, and floor planning.
• Experience with NIC, switch, or storage product development.
• Familiarity with working in design and verification workflows in a CI/CD environment.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.