Principal/ Senior Principal ASIC Architect

Israel

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal/ Senior Principal ASIC Architect to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the architectural definition of cutting-edge connectivity solutions that power the world's largest AI clusters.

As a Principal/ Senior Principal ASIC Architect, you will be the blueprint creator for the future of AI infrastructure. You won't just follow specifications—you will lead the definition and execution of next-generation ASIC solutions targeting hyperscale data centers. From analyzing market requirements to guiding products through their entire lifecycle, your influence will be etched into the silicon that enables the next era of scale-up and scale-out connectivity. If you thrive on solving complex, unnamed challenges and want to shape the architectural foundation of AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

  • Architectural Definition & Strategy

    • Lead the architectural definition of next-generation ASICs, translating complex market requirements into elegant, high-performance hardware specifications
    • Drive technical decision-making that balances power, performance, area, and cost (PPAC) to maintain competitive edge in the hyperscale ecosystem
    • Leverage deep domain expertise to integrate industry standards (Ethernet, UALink, PCIe) into cohesive systems solving demanding AI infrastructure challenges

  • Product Lifecycle Ownership

    • Own the architectural journey from initial concept through design, implementation, tapeout, and mass production
    • Ensure final products deliver on performance promises and meet hyperscaler requirements
    • Drive architectural exploration and performance modeling to validate design decisions

  • Technical Leadership & Cross-Functional Collaboration

    • Act as the technical North Star for the engineering organization in Israel
    • Collaborate across Architecture, Design, Verification, DFT, and Backend teams to ensure seamless execution
    • Influence and align cross-functional teams around unified technical vision through strong communication and leadership

Basic Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Science, or related technical field
  • 12+ years of proven success as an ASIC/Chip Architect or System-Level Integrator at semiconductor companies
  • Demonstrated background in networking domain with deep familiarity with Ethernet standards
  • Proven track record delivering complex hardware designs from high-level definition through successful tapeout and high-volume production
  • Strong communication and interpersonal skills with ability to influence cross-functional teams
  • Experience making architectural trade-offs balancing power, performance, area, and cost

Preferred Qualifications

  • Master's degree in Electrical Engineering, Computer Science, or related technical field
  • Deep understanding of UALink, CXL, or other AI-specific interconnect protocols
  • Knowledge of AI/ML workload requirements and their impact on rack-scale connectivity
  • Expertise in high-speed serial protocols and low-latency interconnects
  • Experience with performance modeling and architectural exploration tools

 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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