Senior DFT Design Engineer

About Celestial AI

As Generative AI continues to advance, the performance drivers for data center infrastructure are shifting from systems-on-chip (SOCs) to systems of chips. In the era of Accelerated Computing, data center bottlenecks are no longer limited to compute performance, but rather the system’s interconnect bandwidth, memory bandwidth, and memory capacity. Celestial AI’s Photonic Fabric™ is the next-generation interconnect technology that delivers a tenfold increase in performance and energy efficiency compared to competing solutions.

The Photonic Fabric™ is available to our customers in multiple technology offerings, including optical interface chiplets, optical interposers, and Optical Multi-chip Interconnect Bridges (OMIB). This allows customers to easily incorporate high bandwidth, low power, and low latency optical interfaces into their AI accelerators and GPUs. The technology is fully compatible with both protocol and physical layers, including standard 2.5D packaging processes. This seamless integration enables XPUs to utilize optical interconnects for both compute-to-compute and compute-to-memory fabrics, achieving bandwidths in the tens of terabits per second with nanosecond latencies.

This innovation empowers hyperscalers to enhance the efficiency and cost-effectiveness of AI processing by optimizing the XPUs required for training and inference, while significantly reducing the TCO2 impact. To bolster customer collaborations, Celestial AI is developing a Photonic Fabric ecosystem consisting of tier-1 partnerships that include custom silicon/ASIC design, system integrators, HBM memory, assembly, and packaging suppliers.

ABOUT THE ROLE

We are looking for an experienced Senior DFT Design Engineer to develop and implement advanced Design-for-Test (DFT) strategies for complex digital designs on deep technology nodes. This role is crucial in ensuring high-quality silicon production, with focus on pre-silicon design as well as post-silicon bring-up, debug, and production release for Known Good Die (KGD).

If you have expertise in DFT methodologies—including scan, MBIST, ATPG, functional and AMS testing, and test compression—along with hands-on experience in post-silicon validation and production test optimization, we want to hear from you.

ESSENTIAL DUTIES AND RESPONSIBILITIES

• Develop and implement DFT methodologies for complex ASICs and SoCs, ensuring high test coverage and manufacturability.
• Design, integrate, and validate scan chains, compression techniques, MBIST, and ATPG patterns for manufacturing tests.
• Perform post-silicon bring-up, debug, and production release for KGD, working closely with test and product engineering teams.
• Optimize test time, fault coverage, and yield using advanced test time reduction strategies and fault coverage analysis.
• Collaborate with cross-functional teams—including design, verification, and test engineering—to define and implement DFT requirements from early design through production.
• Work with foundries and test vendors to ensure seamless production test flow, yield optimization, and failure analysis.
• Select and integrate EDA DFT tools, ensuring an efficient and scalable DFT implementation process.
• Provide technical leadership and mentorship to junior engineers, fostering a strong DFT culture within the team.

QUALIFICATIONS

• Bachelor’s degree with 8+ years of experience, or Master’s degree with 6+ years of experience in Computer Science, Electrical Engineering, Information Technology or a related technical field
• 8+ years of hands-on experience in DFT design with a proven track record of silicon success.
• Proficiency in Mentor Tessent, as well as other industry-leading EDA tools.
• Strong expertise in DFT design as well as post-silicon validation, debug, failure analysis, and production release for KGD.
• Deep understanding of ATPG, MBIST, scan insertion, JTAG, IEEE 1500, boundary scan techniques, functional test methodologies, and AMS test strategies.
• Experience with test time optimization, fault coverage analysis, and test vector generation.
• Strong scripting skills in Tcl, Perl, and Python for automation and workflow optimization.
• Knowledge of formal verification techniques for DFT and power-aware DFT strategies.
• Strong communication and collaboration skills to work effectively across design, verification, and test engineering teams.

LOCATION: Orange County, CA 

For California Location:

As an early stage start up, we offer an extremely attractive total compensation package inclusive of competitive base salary, bonus and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $185,000.00 - $225,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews. 

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.

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