Test Architect / Principal Test Engineer — Optical Engine

Cspeed IO is a stealth start up backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA.  Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.

Cspeed IO is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures.  Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.

The Role

This position owns test strategy for CspeedIO optical engines, from wafer-level probe through final engine test. The strategy is to be defined rather than inherited.

An optical engine is a multi-die assembly integrating a photonic IC, an electronic IC, and a light source die. Each die carries substantial unit cost, and a defect in any one compromises the completed assembly. Known-good-die confidence must therefore be established before permanent bonding — a requirement that conventional electrical test methods cannot satisfy on an electro-optical platform.

The role determines what is tested at each insertion, the coverage each insertion delivers, its cost, and where residual risk is accepted. It then establishes the capability to execute that strategy, both in-house and at our assembly and test partners.

Responsibilities

Test strategy and architecture

• Define the end-to-end test flow across all insertions: PIC wafer-level electro-optical probe, EIC wafer sort, light source die screening, post-bond subassembly, engine-level final test, and reliability sampling.
• Establish the known-good-die strategy for each die type, including achievable coverage, cost per unit, and the escape rate accepted at each gate.
• Maintain the test cost and coverage trade model supporting product cost targets, updating it as the architecture evolves.
• Drive design-for-test requirements into the PIC, EIC, and package — loopback structures, on-die monitors, probe pad and optical port placement, JTAG and serial access, and test-mode definition — with the objective of closing DFT gaps before first build.

Test development and hardware

• Specify and bring up test hardware: probe cards, optical probe and fiber alignment solutions, load boards, sockets, thermal control, and engine-level fixtures.
• Develop test programs and measurement methodologies for the required parameters, including insertion and coupling loss, per-channel optical power and wavelength, extinction ratio, responsivity, dark current, BER and PAM4 eye performance, light source LIV and spectral behavior, and thermal response.
• Establish correlation between bench characterization, production test, and system-level behavior, such that engine-level results predict performance in a customer platform.

Manufacturing and vendor execution

• Transfer test flows to our OSATs and test houses, owning the test specification, release package, gauge studies, and lab-to-floor correlation.
• Evaluate and select test equipment and partners, including ATE, optical probe stations, and fiber attach and alignment platforms.
• Establish SPC, yield reporting, and die-level traceability. Define the data model and lead selection and deployment of MES/YMS tooling for unit-level genealogy across a multi-die assembly.

Yield and failure analysis

• Lead root-cause analysis of electro-optical failures spanning die, package, bond interface, and fiber attach, including failures that cross domain boundaries.
• Direct yield learning with the packaging, photonics, and IC design teams, and with OSAT process owners.
• Own qualification and reliability test planning (HTOL, temperature cycling, damp heat, mechanical) and support customer audits.

Required Qualifications

• MS or PhD in Electrical Engineering, Optics, Physics, or equivalent practical background.
• 10+ years in test engineering for photonic, optoelectronic, or high-speed mixed-signal products, including ownership of at least one flow taken from development into production.
• Demonstrated ownership of test strategy definition rather than execution alone, including accountability for a coverage-versus-cost position.
• Working knowledge of ATE platforms and production test program development, with proficiency in Python (or LabVIEW/C#) for instrument control, automation, and data analysis.
• Statistical competence: SPC, gauge repeatability, and capability analysis, including the ability to distinguish part variation from measurement variation.
• Experience managing OSATs or external test houses across multiple time zones, in English.

Preferred Qualifications

• Direct silicon photonics test experience: wafer-level electro-optical probe, grating or edge-coupler probing, and double-sided probe approaches.
• Hands-on depth with optical test instrumentation: tunable lasers, optical spectrum analyzers, power meters, BERTs, high-speed sampling scopes, and automated fiber alignment.
• Known-good-die methodology for multi-die or chiplet assemblies, and familiarity with 2.5D/3D packaging test constraints.
• Transceiver or optical engine background, with familiarity with IEEE 802.3, OIF, and CMIS-adjacent requirements.
• Experience deploying MES/YMS or die-traceability platforms in a low-volume-to-ramp environment.
• First-generation product or startup experience, where no established test flow or vendor reference process existed.

Scope and Impact

The known-good-die strategy defined in this role determines whether the product is economically manufacturable. It represents the largest single cost and yield lever in the engine and is currently unresolved. The position operates at the intersection of photonic design, package assembly, and OSAT process execution, and sets the criteria by which a completed engine is judged acceptable.