Principal Engineer - DFT

Company Overview

Ambiq is on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

Ambiq is seeking an experienced Principal DFT (Design for Testability) Engineer to lead the architecture, implementation, and continuous improvement of DFT solutions across our ultra-low-power SoC portfolio.

This is a highly hands-on technical leadership role for an engineer who can operate across the complete DFT lifecycle—from architecture and RTL integration through scan insertion, ATPG, MBIST, verification, silicon bring-up, and production test. The Principal DFT Engineer will serve as a key technical authority for DFT methodology, working closely with RTL design, verification, physical design, STA, and test engineering teams to ensure Ambiq products meet aggressive testability, quality, yield, power, and manufacturing-cost objectives.

The successful candidate will initially be expected to contribute directly to implementation while helping evolve Ambiq's DFT architecture, infrastructure, and methodology across multiple concurrent SoC programs.

Responsibilities

• Lead DFT architecture, implementation, and methodology across complex ultra-low-power SoCs.

• Own hands-on implementation using Cadence Genus and Modus Compression, including low-power scan insertion, compression, ATPG pattern generation, debug, and coverage closure.

• Define and implement hierarchical DFT architectures across blocks, subsystems, and full-chip SoCs.

• Implement and optimize scan architectures including stuck-at, at-speed, path-delay, scan compression, boundary scan, and JTAG.

• Develop and implement low-power DFT architectures and methodologies appropriate for Ambiq's ultra-low-power SoCs.

• Lead MBIST architecture, implementation, verification, and memory repair methodology using Tessent MBIST.

• Plan, generate, verify, and deploy memory repair patterns for production.

• Generate structural test vectors and drive improvements in fault coverage, pattern count, test time, test power, and manufacturing cost.

• Develop and debug ATPG and MBIST test environments and perform pre-layout and post-layout gate-level simulations.

• Partner closely with RTL designers to identify and resolve logical and architectural DFT issues.

• Work with STA and physical design teams to resolve DFT-related timing, clocking, congestion, power, and implementation challenges.

• Define and review timing constraints associated with scan, ATPG, MBIST, and test modes.

• Support silicon bring-up and partner with test engineering on production test program development and pattern deployment.

• Analyze ATE failure data and perform ATPG-based diagnosis and root-cause analysis.

• Develop automation and infrastructure using Tcl, Perl, Python, or similar scripting languages.

• Drive continuous improvement of DFT flows, automation, methodologies, and best practices across Ambiq's product portfolio.

• Serve as a technical authority for complex DFT issues and provide technical guidance and mentorship to engineers across the organization.

• Influence early SoC architecture decisions to ensure testability, power, performance, physical implementation, and manufacturing requirements are considered from the beginning of the design cycle.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field.

• Typically 15+ years of progressive hands-on DFT implementation and architecture experience with complex SoCs.

• Hands-on expertise with Cadence Genus and Cadence Modus Compression is required.

• Demonstrated ability to independently develop, implement, debug, and optimize Genus/Modus-based DFT flows.

• Deep expertise in scan insertion, ATPG, scan compression, stuck-at, at-speed, path-delay, boundary scan, JTAG, and MBIST.

• Proven experience defining and implementing hierarchical DFT architectures for complex multi-block SoCs.

• Strong experience with Tessent MBIST, including memory test architecture, memory repair, pattern generation, and verification.

• Strong low-power DFT experience, including power-aware scan and ATPG methodologies.

• Strong RTL design and debug skills with the ability to trace DFT issues from gate-level implementation back into RTL.

• Extensive knowledge of STA, timing concepts, SDC constraints, clocking, and test-mode timing closure.

• Experience developing ATPG and MBIST testbenches and performing pre-layout and post-layout gate-level simulations.

• Experience optimizing test coverage, test time, test power, and pattern count for production.

• Experience supporting silicon bring-up and production test programs.

• Experience analyzing ATE failure data and performing diagnosis using ATPG tools.

• Strong scripting and automation skills using Tcl and Python and/or Perl.

• Demonstrated ability to solve complex technical problems spanning DFT, RTL, STA, physical design, verification, and silicon test.

• Proven ability to influence technical direction and mentor other engineers while remaining highly hands-on.

• Excellent written and verbal communication skills.

Preferred Qualifications

• Experience developing DFT for ultra-low-power MCUs or SoCs.

• Experience with multi-voltage and multi-power-domain designs.

• Experience with power-aware ATPG, scan-power optimization, and IR-drop considerations during test.

• Experience with advanced DFT automation and methodology development.

• Experience supporting multiple SoC programs or product families concurrently.

• Experience establishing or significantly improving an organization's DFT architecture, infrastructure, or methodology.

Location

This position is based in NW Austin, Texas and requires working onsite 5 days per week.

Work Authorization

Candidates must be currently authorized to work in the United States for any employer. Ambiq does not sponsor or take over sponsorship of employment visas for this role now or in the future.