Principal STA Engineer - DFT Focus

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. 

Job Summary:
As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure.

Key Responsibilities:

• Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets.
• Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime.
• Analyze and resolve timing violations, with a focus on test modes and scan paths.
• Integrate and validate timing constraints from third-party IPs and external vendors.
• Generate detailed timing reports, highlighting violations and providing optimization recommendations.
• Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues.
• Contribute to the development and enhancement of STA methodologies, flows, and automation.
• Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision.
• Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind.
• Collaborate effectively with cross-functional and globally distributed teams.

Basic Qualifications:

• Bachelor’s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master’s degree with 6+ years.
• Proven experience with block- and full-chip timing constraints, including test modes.
• Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT.
• Experience integrating third-party IPs and managing associated timing constraints.
• Proficiency in STA tools such as PrimeTime and scripting for automation.

Preferred Qualifications:

• Experience with automated constraint generation and validation tools.
• Familiarity with high-speed interfaces such as PCIe, CXL, and DDR.
• Strong communication and collaboration skills in cross-functional, globally distributed teams.

 Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.  

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.