Principal Package SIPI Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com.

Job Description:              

As a Principal Package SIPI Engineer at Astera Labs, you will lead the development of IC packaging solutions with a primary focus on Signal and Power Integrity (SIPI). Your primary responsibility will be developing and validating electrical models to optimize and ensure robust SIPI performance across chip–package–PCB interfaces. You will drive co-design efforts, perform simulation and correlation, optimize package design, and influence substrate architecture to enable next-generation connectivity products. This role requires close collaboration with silicon, layout, hardware, and manufacturing teams to meet electrical, cost, and production goals while advancing SIPI methodologies and ensuring first-pass success.

Basic qualifications:

• MS or PhD in Electrical Engineering or related field.
• 8+ years of progressive experience in Signal and Power Integrity (SIPI) modeling, analysis, and optimization across the chip–package–board system.
• Expert-level proficiency in EM extraction and modeling using tools such as ANSYS HFSS, SIwave, 3DLayout, Keysight ADS, and ability to develop accurate end-to-end SI/PI models for system-level simulation and tape-out.
• Experience in developing high-performance packages such as FCBGA/FCCSP and advanced packages such as chiplet and 2.5D with the focus on SIPI.
• Experience in developing IC packages for 200G/400G connectivity, targeting PCIe, Ethernet, or other high-speed SerDes protocols, with emphasis on signal integrity.
• Demonstrated success in leading cross-functional efforts from early package concept to production ramp, collaborating with internal architecture, silicon, and board design teams as well as external substrate and OSAT partners.
• A strategic and hands-on mindset with a strong sense of ownership and initiative to deliver IC package solutions that meet SIPI requirements and all specifications on schedule.

Required experience:

• Deep experience in extracting and analyzing package S-parameter model for high-speed interfaces.
• Expert in PDN design and analysis, including DC IR drop, loop inductance, target impedance, AC transient behavior, and chip-package-model (CPM).
• Hands-on experience in chip–package–board co-design and optimization, using system-level tools such as Keysight ADS or equivalent (e.g., power-aware SI simulation, eye diagram, ERL, transient response, etc.).
• Deep understanding of design tradeoffs in SIPI performance vs. cost, manufacturability, and reliability.
• Demonstrated ability to correlate simulation to measurement, refine models, and improve model-to-measurement accuracy.
• Familiarity with lab measurement and correlation workflows, including VNA, TDR, and high-speed oscilloscope-based validation.
• Strong understanding of package technologies including FCCSP, FCBGA, with exposure to substrate stack-up design, bump/RDL planning, and design for reliability and manufacturability (DFR, DFM).
• Experience engaging directly with substrate vendors and OSATs, including design reviews, technical deep dives, and yield/ramp-up issue resolution.

 Preferred experience:

• Experience in scripting language (such as python / ironpython) for modeling automation is a plus.
• Contributions to SIPI methodology development, internal training, or industry publications/patents are a plus.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.