Current openings at Phizenix

We are seeking an experienced Package Reliability Engineer with expertise in 2.5D/3D advanced packaging. The ideal candidate will have a strong background in physics of failure, materials science, and experience working closely with OSATs to drive package reliability improvements. This role requires collaboration with external assembly and test partners, internal design, process, and failure analysis teams, and suppliers to ensure the reliability and manufacturability of cutting-edge semiconductor packages. ESSENTIAL DUTIES AND RESPONSIBILITIES Reliability Analysis & Risk Assessment: Conduct physics of failure (PoF)-based reliability modeling for 2.5D/3D advanced packaging. Assess package reliability risks from thermal, mechanical, and electrical stressors. Define and execute stress test plans (e.g., thermal cycling, humidity, electromigration) to validate package robustness. OSAT Management & Collaboration: Work closely with OSAT partners to drive package reliability improvements, process optimizations, and yield enhancements. Define reliability requirements, review test methodologies, and ensure OSAT compliance with JEDEC and industry standards. Monitor and evaluate OSAT performance in executing reliability qualifications and failure analysis. Support supplier audits and technical reviews to assess manufacturing capabilities and reliability processes. Material Characterization & Selection: Evaluate and select materials (substrates, dielectrics, adhesives, underfills) for optimal reliability. Analyze CTE mismatches, warpage, delamination, and interfacial adhesion issues. Work with material suppliers and OSATs to qualify new materials for advanced packaging applications. Failure Analysis & Root Cause Identification: Lead failure mode analysis (FMEA), model-based problem solving (MBPS) and determine root causes of package failures using techniques such as FIB, X-ray, SEM, and TEM. Identify and mitigate interfacial failures, cracking, voiding, electromigration, and stress-induced damage. Drive OSATs and internal teams to implement corrective and preventive actions (CAPA). Process & Design Collaboration: Work cross-functionally with internal design, process, and manufacturing teams to define assembly test vehicles and optimize package architectures. Develop and refine design guidelines, process improvements, and reliability best practices. Stay up to date with industry standards (JEDEC, IPC, IEEE, etc.) and implement best practices in package reliability. QUALIFICATIONS Education: Master’s or Ph.D. in Materials Science, Mechanical Engineering, Electrical Engineering, Applied Physics, or a related field. Experience: 5-10 years of hands-on experience in 2.5D/3D advanced packaging reliability. Technical Expertise: Deep understanding of physics of failure (PoF) methodologies for package reliability. Strong knowledge of materials science, particularly in interconnects, substrates, and interfaces. Proficiency in stress modeling tools (ANSYS, Abaqus, COMSOL, etc.) for thermo-mechanical analysis. Experience with failure analysis techniques such as C-SAM, X-ray CT, SEM, TEM, FIB, and EBSD. OSAT Collaboration Experience: Proven track record of working with and driving OSAT partners for package reliability, yield, and continuous quality improvements. Experience managing OSAT qualifications, failure analysis, and corrective actions. Familiarity with supplier engagement, reliability testing at OSATs, and package process flows. Industry Knowledge: Familiarity with JEDEC, IPC, IEEE, and MIL-STD reliability standards. Soft Skills: Strong analytical, problem-solving, and cross-functional collaboration skills.   PREFERRED QUALIFICATIONS Experience in heterogeneous integration, fan-out packaging, chiplet architectures. Knowledge of electrical reliability mechanisms (e.g., electromigration, time-dependent dielectric breakdown). Expertise in AI-driven reliability modeling or machine learning for failure prediction.

Role Overview Lead silicon bring-up, post-silicon validation, and deep debug of next-generation AI accelerator chiplets, including validation of high-speed interfaces such as PCIe Gen5, LPDDR5, and die-to-die interconnects. Define and execute comprehensive validation and bring-up strategies, building automated, self-checking test frameworks with firmware- and kernel-level instrumentation and logging. Develop embedded firmware and host-side test software to stress, validate, and characterize high-speed interfaces across multiple system configurations. Work hands-on in the lab, partnering with the team to set up and utilize advanced debug and test equipment to support efficient validation and issue resolution. Collaborate closely with hardware, software, validation, test, and operations teams, including support for ATE and complex HW/SW debug efforts. Qualifications BS/MS in Electrical or Computer Engineering with 15+ years of experience working on high-performance SoCs. Proven experience in system and AI accelerator bring-up and post-silicon debug. 5+ years of embedded software, firmware, or RTOS development experience. Strong familiarity with high-speed serial protocols (PCIe Gen3/4/5) and/or high-speed memory technologies (LPDDR3/4/5 or similar I/O standards). Excellent debugging, communication, and cross-functional collaboration skills, with the ability to work effectively across diverse engineering teams.