Job
AI/ML Physical Design Flow Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Full-Chip Physical Design Verification Engineer
Physical Design Engineer, PnR
Physical Design Engineer - STA
Staff Engineer, Physical Design
Staff Technical Program Manager, Physical Design
Top Level Physical Design Engineer
Design Verification Lead, AI Hardware
Toronto, Ontario, Canada
Director, Customer Hardware Engineering
Performance Architect, AI HW
Staff Design Verification Engineer, AI HW
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada; Zürich, Switzerland
AI Hardware
Physical Design Engineer, AI Accelerator IP
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada
Physical Design Methodology Engineer, AI HW IP
Senior Embedded Engineer, AI IP
Belgrade, Serbia; Toronto, Ontario, Canada
Power Architect
Santa Clara, California, United States
Principal CPU Microarchitect - RISC-V & AI Compute
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada
Staff Engineer, RTL Design AI Hardware
Belgrade, Serbia
C++ Machine Learning Engineer, Models Training
Gdańsk, Pomeranian Voivodeship, Poland; Warszawa, Masovian Voivodeship, Poland
Software Engineer, Acceleration Kernel Development
AI SW
Staff Software Engineer, Cloud Infrastructure
Sr. Network Engineer
Systems Engineer, Data Center Debug
Staff Debug and DevOps Engineer
Machine Learning Engineer, AI Models
Cyprus
Machine Learning Research Engineer (LLMs & AI Systems)
Boston, Massachusetts, United States; Toronto, Ontario, Canada
Software Engineer-AI Model Bring Up
Tokyo, Japan
Acceleration Kernel Developer Lead
Sr. Engineer, Kernel Development and Optimization
GCC Compiler Engineer
Software Engineer, Metal Runtime (Core Systems)
Software Engineer, Scale Out
Software Engineer, TT-Distributed
Software Engineer, TT-Fabric
Staff Technical Program Manager, Agentic Workflows & Program Intelligence
Technical Program Manager, Product Software
Chiplet Physical Design Engineer
DFT Engineer
Fabric SOC Architect
Interconnect and Compute Architect
RISC-V AI / HPC & Agentic Software Engineer
新北市, New Taipei City, Taiwan
RISC-V AI / HPC & Agentic Software Engineering Lead
Senior DFT Engineer, Architecture
Verification Engineer
Japan
Architecture
Chiplet Design Architect
CPU Microarchitect, Vector and Matrix Compute
Santa Clara, California, United States; Spain
RISC-V CPU Microarchitecture / RTL
CPU Verification Fellow, RISC-V High-Performance Processor
Austin, Texas, United States; Santa Clara, California, United States
CPU Architect, Load-Store
Sr. Performance Modeling Architect
Technical Program Manager, Architecture
