Customer
Job
Field Application Engineer - AI Software & Hardware
Europe; Munich, Germany
Customer - Operations
Design Verification Engineer, Automotive Robotics
Munich, Germany
DFT Engineer, Automotive Robotics
Emulation Engineer, Automotive Robotics
SOC Architect - Chiplet
Engineering - Hardware
AI/ML Physical Design Flow Engineer
Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States
Full-Chip Physical Design Verification Engineer
Physical Design Engineer, PnR
Physical Design Engineer - STA
Staff Engineer, Physical Design
Staff Technical Program Manager, Physical Design
Top Level Physical Design Engineer
Design Verification Lead, AI Hardware
Toronto, Ontario, Canada
Director, Customer Hardware Engineering
Performance Architect, AI HW
Senior Engineer, System-Level Design Verification
Sr Engineer, AI Kernel
Austin, Texas, United States; Santa Clara, California, United States; Toronto, Ontario, Canada
Staff Design Verification Engineer, AI HW
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada; Zürich, Switzerland
Engineering - Hardware / AI Hardware
Physical Design Engineer, AI Accelerator IP
Austin, Texas, United States; Belgrade, Serbia; Toronto, Ontario, Canada
Physical Design Methodology Engineer, AI HW IP
Senior Embedded Engineer, AI IP
Belgrade, Serbia; Toronto, Ontario, Canada
Power Architect
Principal CPU Microarchitect - RISC-V & AI Compute
Staff Engineer, RTL Design AI Hardware
Belgrade, Serbia
Chiplet Physical Design Engineer
Santa Clara, California, United States
DFT Engineer
Engineer, SoC RTL Engineer
Tokyo, Japan
Fabric SOC Architect
Interconnect and Compute Architect
Power Design Engineer
RISC-V AI / HPC & Agentic Software Engineer
新北市, New Taipei City, Taiwan
RISC-V AI / HPC & Agentic Software Engineering Lead
Senior DFT Engineer, Architecture
Verification Engineer
Japan
Engineering - Hardware / Architecture
Technical Program Manager, Architecture
Automotive and Robotics SOC Architect
Chiplet Design Architect
CPU Microarchitect, Vector and Matrix Compute
Santa Clara, California, United States; Spain
RISC-V CPU Microarchitecture / RTL
CPU Verification Fellow, RISC-V High-Performance Processor
CPU Architect, Load-Store
Sr. Performance Modeling Architect
Austin, Texas, United States; Santa Clara, California, United States
CPU Core Design Verification Testbench Lead
CPU Core Design Verification Test Generator Lead
Director, RISC-V Software TPM & Ops
Australia; Santa Clara, California, United States
Engineering Program Manager, RISCV
Austin, Texas, United States
(India) System IP Design Engineer
Bengaluru, Karnataka, India
Sr. Engineer, CPU RTL Design
Sr. Engineer, Performance Infrastructure
Sr. Staff Engineer, RISC-V Software Workload Enablement
