Staff, System IP Design Verification Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We're looking for a passionate and hands-on RISC-V System IP DV Engineer to architect, develop, and evolve world-class verification infrastructure for System IPs (interrupt controllers, IOMMU, power management, DFD etc) that will be integrated in high-performance RISC-V CPU clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

• You bring domain understanding of power management flows like clocks, resets, low power states, system management controller interactions etc
• You thrive in building robust verification environments using SystemVerilog and UVM, and optionally C++, and can define and drive verification plans independently.
• You have a strong grasp of stimulus planning, checker development, debug techniques, and coverage closure for verifying complex hardware subsystems.
• You’re comfortable working on features that span multiple IPs and can devise plans to verify them at IP, subsystem and fullchip levels.

What We Need

• A Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Strong experience with System Verilog and UVM-based verification.
• Proven ability to drive IP level and subsystem level DV projects.
• Familiarity with power management flows, hardware/firmware interactions, bus protocols like AXI.

What You Will Learn

• Owning a large scope with a small focused team.
• How to structure and deliver an IP/kit to SoCs with seamless integration in mind.
• How power management impacts the entire SoC, collaborating closely with RTL designers, architects, firmware engineers etc.
• Building reusable verification components, coverage models, and checkers that scale across multiple abstraction layers.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology.  Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).   These requirements apply to persons located in the U.S. and all countries outside the U.S.  As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.  If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.