Staff, Design Verification Engineer – CPU Cluster

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We're looking for a passionate and hands-on RISC-V CPU Cluster/SoC DV Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V cores and clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

• Skilled in building robust verification environments with System Verilog, UVM, and C++, and confident driving verification plans independently.
• Bring a system-level mindset with experience integrating and verifying multi-IP clusters or SoCs.
• Strong in stimulus planning, debug, and coverage closure for subsystems like caches, NoCs, and memory hierarchies.
• Comfortable working on cross-IP features such as coherence and security at the cluster or SoC level.

What We Need

• Bachelor’s or Master’s in Electrical Engineering, Computer Science, or a related field.
• Hands-on experience with System Verilog and UVM-based verification.
• Track record of driving subsystem or SoC-level DV projects, including integration and feature validation.
• Familiarity with AXI/CHI protocols, system IPs (debug, power mgmt), and multi-IP verification flows.

What You Will Learn

• How to scale DV infrastructure for high-performance RISC-V clusters and SoCs.
• Verification strategies for multi-agent systems across CPUs, IPs, and interconnects.
• Best practices for integration-level planning and cross-IP feature convergence.
• Collaborating across RTL, DV, software, and validation teams to drive system-level bring-up.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set  by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government.  If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.